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Process flow and manufacturing concept for embedded active devices

: Aschenbrenner, R.; Ostmann, A.; Neumann, A.; Reich, H.

Toh, K.C. ; Institute of Electrical and Electronics Engineers -IEEE-, Singapore Section; IEEE Components, Packaging, and Manufacturing Technology Society; International Microelectronics and Packaging Society -IMAPS-:
6th Electronics Packaging Technology Conference, EPTC 2004. Proceedings : 8 - 10 December 2004, Pan Pacific Hotel, Singapore
Piscataway, NJ: IEEE Service Center, 2004
ISBN: 0-7803-8821-6
ISBN: 0-7803-8822-4
Electronics Packaging Technology Conference (EPTC) <6, 2004, Singapore>
Fraunhofer IZM ()

The development of smaller, lighter and thinner packages with larger and higher pin count IC's and better performance will play an enourmously important role in the future for portable electronic products. Additionally the product life time is going down, requiring short design cycles and a production at low-cost based on well established technologies. These trends are a strong challenge for microelectronic packaging and assembly technology. A chip embedding technology for stackable packages was developed at the joined institute of Fraunhofer IZM and the Technical University of Berlin the so called Chip in Polymer (CIP) process. Its main feature is the emdedding of very thin chips (50 m thickness or less) into build-up layers of printed circuit boards (PCB's), which does not sacrifice any space in the core substrate. The embedded chips can be combined with integrated passive components. A substantial advantage of the CIP approach is the embedding of components, using ma inly processes and equipment from advanced PCB manufacturing. The scope of this paper is the presentatiom of the Chip in Polymer technology regarding technological and economical aspects and to discuss the effect on a new value chain.