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Electrical Measurement of alignment for 3D stacked chips

: Canegallo, R.; Mirandola, M.; Fazzi, A.; Magagni, L.; Guerrieri, R.; Kaschlun, K.


Fesquet, L.:
ESSCIRC 2005, 31st European Solid-State Circuits Conference. Proceedings
Piscataway, NJ: IEEE Operations Center, 2005
ISBN: 0-7803-9205-1
European Solid State Circuits Conference (ESSCIRC) <31, 2005, Grenoble>
Fraunhofer IZM ()

This paper presents an electronic system based on integrated CMOS capacitive sensors that enables to determine the alignment between two chips assembled in a three-dimensional (3D) stacking configuration. Two different interface circuits are described for the on-chip measurement of alignment along vertical Z-axis and lateral X/Y-axis. A test chip has been fabricated in 0.13m, 6 metal standard CMOS process to test the multi-axis alignment system based on 3D sensors. A capacitive charge variation of 1fF over 15fF corresponding to a resolution accuracy of 0.5m over a range of 50m has been measured. Sensors are 120m × 30m and power consumption is 200W.