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A 0.14mW/Gbps high-density capacitive interface for 3D system integration

: Fazzi, A.; Magagni, L.; Mirandola, M.; Canegallo, R.; Schmitz, S.; Guerrieri, R.


IEEE Solid-State Circuits Society:
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference : September 18 - 21, 2005, San Jose, California
Piscataway, NJ: IEEE Operations Center, 2005
ISSN: 08865930
ISBN: 0780390237
ISBN: 9780780390232
Annual IEEE Custom Integrated Circuits Conference (CiCC) <27, 2005, San Jose>
Fraunhofer IZM ()

This paper presents a synchronous 3D interconnection based on capacitive coupling. The designed link presents a power consumption of 0.128mW/pin@975Mbps/ pin, overcoming standard I/O pads performance of two orders of magnitude. High bit-rate, reduced power consumption and electrode area down to 8×8m2 enable the implementation of highly parallel pipelined interfaces for inter-chip communication, with an aggregate consumption of about 0.14mW/Gbps. ©2005 IEEE.