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Thin hermetic passivation of semiconductors using low temperature borosilicate glass - Benchmark of a new wafer-level packaging technology

: Leib, J.; Gyenge, O.; Hansen, U.; Maus, S.; Fischer, T.; Zoschke, K.; Toepper, M.


Institute of Electrical and Electronics Engineers -IEEE-:
IEEE 59th Electronic Components and Technology Conference, ECTC 2009. Vol.2 : San Diego, CA, USA, 26 - 29 May 2009
New York, NY: IEEE, 2009
ISBN: 978-1-4244-4475-5
ISBN: 978-1-4244-4476-2
Electronic Components and Technology Conference (ECTC) <59, 2009, San Diego/Calif.>
Fraunhofer IZM ()

A novel approach on wafer-level passivation using a thin, hermetic borosilicate glass layer replacing the polymers in redistribution is presented here. The technology will be benchmarked to those conventional technologies. The glass layer is deposited at low temperatures (T < 100°C) using a plasma-enhanced e-beam deposition and can be structured by a lift-off process using a standard photo resist process for masking. The process flow is fully compatible with standard CMOS post processing and is integrated in a state-of-the-art production environment.