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Hotspot-optimized interlayer cooling in vertically integrated packages

: Brunschwiler, T.; Michel, B.; Rothuizen, H.; Kloter, U.; Wunderle, B.; Reichl, H.

Roozeboom, F. ; Materials Research Society -MRS-:
Materials and Technologies for 3-D Integration : Symposium E held December 1-3, 2008, Boston, Massachusetts, U.S.A.
Warrendale, Pa.: MRS, 2009 (Materials Research Society Symposium Proceedings 1112)
ISBN: 978-1-60511-084-4
Symposium E "Materials and Technologies for 3-D Integration" <2008, Boston/Mass.>
Materials Research Society (Fall Meeting) <2008, Boston/Mass.>
Fraunhofer IZM ()

High-performance, vertically integrated chip stacks with multiple logic layers and aligned hot spots, need cooling by an interlayer heat-removal approach. At high interconnect densities, fluid friction increases dramatically, and the most significant portion of the junction temperature rise is due to a sensible heat increase in the fluid. First we introduce three building blocks that extend the interlayer cooling capability to an interconnect pitch less than 100m by considering hot-spot-aware mass and heat transfer. The methods used are hydraulic diameter modulation, four-port fluid access, and fluid focusing. Second, we demonstrate an approach to combine these methods based on an efficient porous-medium approach using expressions for pressure gradients and convective thermal resistances derived from detailed sub-modeling in communicating pin fin array cavities. Finally, three different global heat-transfer layouts are compared.