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Thin hermetic borosilicate glass layers for highly reliable chip-passivations in wafer-level-packaging

: Hansen, U.; Leib, J.; Maus, S.; Gyenge, O.; Töpper, M.

International Microelectronics and Packaging Society -IMAPS-, Italian Chapter; Institute of Electrical and Electronics Engineers -IEEE-:
EMPC 2009, 17th European Microelectronics and Packaging Conference & Exhibition. CD-ROM : June 15th-18th, 2009 , Rimini, Italy
New York, NY: IEEE, 2009
ISBN: 0-615-29868-0
ISBN: 978-0-615-29868-9
ISBN: 978-1-4244-4722-0
European Microelectronics and Packaging Conference and Exhibition (EMPC) <17, 2009, Rimini>
Fraunhofer IZM ()

A technology yielding thin, hermetic borosilicate glass layers at high deposition rates and low substrate temperatures and its potentials for a novel approach on wafer-level passivation is described. The benefits of this CMOS-compatible technology are highlighted, comparing the achievable film characteristics to polymers commonly used for these purposes. The glass layer is deposited at low temperatures (T < 100°C) using a plasma-enhanced e-beam deposition and can be structured by a lift-off process using a standard photo resist process for masking. The process flow is fully compatible with standard CMOS post processing and is integrated in a state-of-the-art production environment.