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Wafer-level glass capping with optical integration

: Hansen, U.; Maus, S.; Leib, J.; Toepper, M.

Courtois, B. ; IEEE Components, Packaging, and Manufacturing Technology Society; Circuits Multi-Projets -CMP-, Grenoble:
Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2010 : Seville, Spain, 5-7 May 2010; including the Conference on CAD, Design and Test and the Conference on Microfabrication, Integration and Packaging
Piscataway/NJ: IEEE, 2010
ISBN: 978-1-4244-6636-8
ISBN: 978-2-35500-011-9
Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP) <2010, Seville>
Fraunhofer IZM ()

A previously described wafer-level packaging (WLP) process allows quasi-hermetic capping of optical devices on wafer level yielding miniaturized glass cavity windows on top of the optical area - at the same time leaving the contact area accessible for standard electrical connections i.e. wire bond. This paper will focus on advancements in integrating coatings, apertures and three-dimensional lensstructures to achieve a functional integration of a packaging technology with optical qualities. The elevated requirements on the used technologies are discussed and shown on a manufactured demonstrator.