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Integration of carrierless ultrathin wafers into a TSV process flow

: Bieck, F.; Spiller, S.; Molina, F.; Töpper, M.; Lopper, C.; Kuna, I.; Fischer, T.; Röder, J.; Dietrich, L.; Tabuchi, T.


Institute of Electrical and Electronics Engineers -IEEE-, Singapore Section, Reliability CPMT EDS Chapter; IEEE Components, Packaging, and Manufacturing Technology Society:
12th Electronics Packaging Technology Conference, EPTC 2010 : Singapore, 8 - 10 December 2010
New York, NY: IEEE, 2010
ISBN: 978-1-4244-8560-4
ISBN: 978-1-4244-8561-1
Electronics Packaging Technology Conference (EPTC) <12, 2010, Singapore>
Fraunhofer IZM ()

This paper presents a new carrierless approach to handling and processing ultra-thin Silicon which is predominantly used in processing Through Silicon Via (TSV) wafers. Currently, the state of the art consists of bonding the wafers having the vias onto a carrier wafer, after which the thinning steps of the wafer and the backside processing, e.g. Redistribution (RDL) or Bumping, are performed. By means of temporarily bonding the wafer to a carrier, the wafer has structural integrity and can be handled and processed at standard equipment. An alternative to the carrier approach is the use of carrierless ultra thin wafers. Here, the wafer is modified mechanically in a way that the wafer is thin and rigid at the same time. This approach has the potential of bypassing the bonding and de-bonding operations. In detail, we will present results on: 200 mm backside processing 200 mm "Via Reveal" process 300 mm mechanical stability Special lithography process for carrierless wafers.