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Characterization and failure analysis of 3D integrated semiconductor devices-novel tools for fault isolation, target preparation and high resolution material analysis

: Altmann, F.; Petzold, M.; Schmidt, C.; Salzer, R.; Cassidy, C.; Tesch, P.; Smith, N.

Electronic Device Failure Analysis Society -EDFAS-, Materials Park/Ohio:
ISTFA 2010, 36th International Symposium for Testing and Failure Analysis. Conference Proceedings : November 14 - 18, 2010, InterContinental Hotel Dallas, [Addison], Dallas, Texas, USA
Materials Park, Ohio: ASM International, 2010
ISBN: 978-1-615-03041-5
ISBN: 1-615-03041-7
International Symposium for Testing and Failure Analysis (ISTFA) <36, 2010, Dallas/Tex.>
Fraunhofer IWM ()

In this paper we will introduce novel methodical approaches for material and failure analysis of 3D integrated devices. The potential and advantages of the new concepts and tools will be demonstrated for flip-chip-like interconnects but in addition, for the first time, for Through Silicon Vias (TSV). The employed techniques combine non-destructive fault localization with efficient and accurate target preparation to get access for following microstructure diagnostics, forming a subsequent failure analysis workflow. The concept presented here involves the application of improved Lock-In Thermography (LIT), and three different innovative concepts of high rate Focused Ion Beam (FIB) techniques.