Publica
Hier finden Sie wissenschaftliche Publikationen aus den Fraunhofer-Instituten. Localization of electrical defects in system in package devices using lock-in thermography
| Institute of Electrical and Electronics Engineers -IEEE-; VDE/VDI-Gesellschaft Mikroelektronik, Mikro- und Feinwerktechnik -GMM-:
3rd Electronics System Integration Technology Conference, ESTC 2010. Proceedings. Vol.1 : Berlin, Germany, 13 - 16 September 2010
New York, NY: IEEE, 2010
ISBN: 978-1-4244-8553-6
ISBN: 978-1-4244-8554-3
S.303-307 |
| Electronics System Integration Technology Conference (ESTC) <3, 2010, Berlin> |
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| Englisch |
| Konferenzbeitrag |
| Fraunhofer IWM () |
Abstract
The paper deals with demonstration of Lock-in Thermography (LIT) as a new key-method for the defect localization in modern microelectronic devices. After an introduction into the operational principle and recent advantages of LIT, three different case studies for defect localization at multi-chip, flip-chip, and stacked die devices will be presented followed by physical root cause analysis, using mechanical cross sectioning and SEM investigations.