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Through wafer interconnects - a technology not only for medical applications

 
: Vogtmeier, G.; Drabe, C.; Dorscheid, R.; Steadman, R.; Wolter, A.

Nino, J.C. ; Materials Research Society -MRS-:
Heterogeneous integration of materials for passive components and smart systems : Symposium held November 27 - 29, 2006, Boston, Massachusetts, U.S.A.; at the 2006 MRS fall meeting
Warrendale, Pa.: MRS, 2007 (Materials Research Society Symposium Proceedings 969)
ISBN: 1-558-99926-4
ISBN: 978-1-558-99926-8
ISSN: 0272-9172
S.47-58
International Symposium W "Heterogeneous Integration of Materials for Passive Components and Smart Systems" <2006, Boston/Mass.>
Materials Research Society (Fall Meeting) <2006, Boston/Mass.>
Englisch
Konferenzbeitrag
Fraunhofer IPMS ()

Abstract
The foremost driver for the development of fully CMOS compatible Through-Wafer Interconnects (TWIs) is the need of very large photodiode arrays for detectors, e.g. in computed tomography applications, The front to backside contact allows the four-side buttable chip placement of the already large chips (20 × 22 mm2). The TWI technology allows an interconnection for chips up to 280 m thickness. This technique does not require any via opening at the font side, thus enabling a metal signal routing on the active side, on top of the interconnection. The application specific optical sensitive front-side of the chip is fully accessible, The production process is separated into three main steps, The first step is the implementation of the special TWI geometry into the CMOS substrate. Depending on the electrical and geometrical requirements of the circuit, different TWI structures are built with deep trenches (up to 280 ), which are passivated and filled with doped poly-silicon, The technologies used in this process, such as DRIE-etching, oxidation and low pressure CVD, are standard CMOS compatible processes, The use of poly-silicon prevents from achieving very low resistivity interconnections but allows the use of all CMOS process steps for an imager production (no temperature limitation - compared to other TWI process flows). The second step is the standard CMOS processing on the substrate already including the TWIs. The third step is a low temperature backside process starting with wafer thinning down to 280 or less to open the implemented TWI structure from the backside, The thickness may be selected depending on the target application. A modified under bump metallization (UBM) process, which could include also re-routing of signals on the backside, concludes the process flow until the solder ball placement, or similar bond connections. The special process flow opens a variety of applications that benefit from the full CMOS compatible processing and the accessible front-side.

: http://publica.fraunhofer.de/dokumente/N-171740.html