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Studies on underfilling components with area array solder terminals in surface mount technology

 
: Schaefer, H.; Maurieschat, U.; Schimanski, H.; Poech, M.H.; Hoefer, E.; Harder, T.

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Institute of Electrical and Electronics Engineers -IEEE-:
4th IEEE International Conference on Polymers and Adhesives in Microelectronics and Photonics 2004 : 12 - 15 September, 2004, Portland, Oregon
Piscataway, NJ: IEEE Operations Center, 2004
ISBN: 0-7803-8744-9
S.153-162
International Conference on Polymers and Adhesives in Microelectronics and Photonics (Polytronic) <4, 2004, Portland>
Englisch
Konferenzbeitrag
Fraunhofer IFAM ()

Abstract
The underfilling of CSP and BGA components with area I array lead free and lead containing solder terminals in surface mount technology has been systematically studied and evaluated. One of the goals of the research was to define the particular requirements that have to be put on CSP/BGA underfill materials and to estimate what level of process reliability for underfilling can be achieved. The knowledge and experience with flip chip underfilling could not be directly transferred to CSP and BGA assemblies due to the differences in material combinations and geometry of the joint gap as well as the differences in the nature and magnitude of the stress. Ageing and stress tests on test assemblies with commercially available and alternative underfill materials highlighted the specific advantages of underfilling CSPs and BGAs. The experimental findings and the simulations results allowed the required property profiles of CSP/BGA underfillers to be defined. From the effects of underfill defects, statements about process reliability could be made.

: http://publica.fraunhofer.de/dokumente/N-170562.html