: Beug, M.F.; Melde, T.; Paul, J.; Knoefler, R.

Abstract
The sidewall gate-etch damage influence on the electrical behavior of 48-nm TaN/Al2O3/SiN/SiO2/Si (TANOS) nand charge-trapping memory cells is investigated in detail. This etch damage occurs at the sidewall of the high work-function TaN metal gate and high-k Al 2O3 blocking-oxide layers and adversely affects the electrical performance and the mechanical stability of small-ground-rule TANOS cells. Both issues could be solved for 48-nm TANOS cells by the introduction of a new integration scheme, which includes a removable encapsulation liner. This SiN liner protects the TaN sidewall from the etch damage during the aggressive Al2O3 high-k etch process. The optimum of the 48-nm electrical cell performance was found for a 4-nm encapsulation liner thickness. In contrast to 48-nm TANOS cells, the encapsulation liner thickness does not affect the electrical performance of large 5- m-long-and-wide memory cells. The memory cell performance dependence on the TANOS liner thickness andmemory cell size is explained by a damaged Al2O3 region approximately 34 nm thick at the block oxide side wall. As a result, the reported etch damage exhibits a new scaling issue for TANOS memory cells around the 20-nm technology node when the total encapsulation liner thickness approaches half of the memory cell length.