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Multi-level hierarchical analogue fault simulation

: Straube, B.; Vermeiren, W.; Spenke, V.


Microelectronics journal 33 (2002), Nr.10, S.815-821
ISSN: 0026-2692
ISSN: 0959-8324
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()
analogue fault simulator; multi-level hierarchical tool; mixed-signal circuit; behavioural model; fault injection; abstraction level; circuit component; fault simulation process; test signal; defect coverage

In this paper the extensions of our analogue fault simulator `aFSIM' to a multi-level hierarchical analogue fault simulation tool are described. Due to these extensions it is now possible to fault-simulate larger analogue circuits. In addition mixed-signal circuits including a not too large amount of digital circuitry can also be fault-simulated. The term `multi-level hierarchical analogue fault simulation' comprises the usage of behavioural models for components together with components described at the transistor-level, fault injection at different abstraction levels, and a hierarchical handling of both different descriptions of the circuit components and faults during the fault simulation process. Multi-level hierarchical analogue fault simulation is an important means to tackle the complexity of analogue circuits for providing test signals with a high fault and defect coverage.