• English
  • Deutsch
  • Log In
    Password Login
    Research Outputs
    Fundings & Projects
    Researchers
    Institutes
    Statistics
Repository logo
Fraunhofer-Gesellschaft
  1. Home
  2. Fraunhofer-Gesellschaft
  3. Artikel
  4. A 20-GHz bipolar latched comparator with improved sensitivity implemented in InP HBT technology
 
  • Details
  • Full
Options
2011
Journal Article
Title

A 20-GHz bipolar latched comparator with improved sensitivity implemented in InP HBT technology

Abstract
A method for improving the sensitivity (or speed) of a master-slave emitter-coupled logic comparator using emitter degeneration resistors is presented. The degeneration resistors in the latching pair reduce the transistor charging time, thus allowing more time for regeneration. Improved and standard comparators were implemented using the InP/GaInAs heterojunction bipolar transistor technology and were tested at a clock rate of 20 GHz. The improved comparator exhibited better sensitivity (by a factor of 1.7) compared to the standard design. A record low-sensitivity value of 10 mV was obtained.
Author(s)
Kraus, S.
Kallfass, I.
Fraunhofer-Institut für Angewandte Festkörperphysik IAF  
Makon, R.E.
Fraunhofer-Institut für Angewandte Festkörperphysik IAF  
Driad, Rachid  
Fraunhofer-Institut für Angewandte Festkörperphysik IAF  
Moyal, M.
Ritter, D.
Journal
IEEE transactions on microwave theory and techniques  
DOI
10.1109/TMTT.2011.2104974
Language
English
Fraunhofer-Institut für Angewandte Festkörperphysik IAF  
Keyword(s)
  • bipolar comparators

  • emitter coupled logic (ECL)

  • heterojunction bipolar transistor

  • latched comparators

  • master-slave comparators

  • sensitivity

  • Cookie settings
  • Imprint
  • Privacy policy
  • Api
  • Contact
© 2024