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Characterization of digital cells for statistical test

: Hopsch, F.; Lindig, M.; Straube, B.; Vermeiren, W.

Postprint urn:nbn:de:0011-n-1610267 (907 KByte PDF)
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Erstellt am: 3.5.2011

IEEE Computer Society, Test Technology Technical Council -TTTC-:
14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and System, DDECS 2011 : April 13 - 15, 2011, Cottbus, Germany; Proceedings
New York, NY: IEEE, 2011
ISBN: 978-1-4244-9753-9
ISBN: 978-1-4244-9754-6
ISBN: 978-1-4244-9756-0
ISBN: 978-1-4244-9755-3 (Print)
International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) <14, 2011, Cottbus>
Konferenzbeitrag, Elektronische Publikation
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()
Monte Carlo fault simulation; defect-oriented test; parameter variation; characterization; statistical test

Integrated circuits necessitate high quality and high yield. Defects and parameter variations are a main issue affecting both aspects. In this paper a method for characterization for statistical test is presented. The characterization is carried out for a set of digital cells using Monte Carlo fault simulation at electrical level. The results show that only a small amount of faults are being manifested as stuck-at faults. Many faults lead to a mix of different behaviours for various test sequences and parameter configurations. For a digital cell, the necessary test sequences for detecting all detectable faults are derived from the simulation results. Since the effort for the characterization is high, first investigations to reduce this effort are presented.