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Title
Halbleiterbauelement und Verfahren zu seiner Herstellung
Date Issued
2009
Author(s)
Patent No
102009024311
Abstract
(A1) Die Erfindung betrifft ein Verfahren zur Herstellung eines Halbleiterbauelementes, in welchem ein eindimensionales Elektronengas ausbildbar ist, welches die folgenden Schritte enthaelt: Bereitstellen eines Substrates mit einer ersten Oberflaeche; Abscheiden einer Maskierungsschicht mit einer ersten Oberflaeche und einer zweiten Oberflaeche, wobei die zweite Oberflaeche der Maskierungsschicht auf der ersten Oberflaeche des Substrates angeordnet ist; Einbringen von mindestens einem Graben in die Maskierungsschicht, welcher bis zur ersten Oberflaeche des Substrates reicht; Einbringen eines Halbleitermaterials in den mindestens einen Graben und Entfernen der ersten Maskierungsschicht. Weiterhin betrifft die Erfindung ein nach diesem Verfahren hergestelltes Halbleiterbauelement.
WO 2010139546 A1 UPAB: 20110111 NOVELTY - The method for producing a semiconductor structural element (10), in which one-dimensional electron gas is developed, comprises providing a substrate (11) having a first surface, separating a masking layer having a first surface and a second surface, where the second surface of the masking layer is arranged on the first surface of the substrate, introducing a trench in the masking layer extending to the first surface of the substrate, and inserting a semiconductor material in the trench by chemical vapor deposition, metalorganic chemical vapor deposition or metalorganic vapor phase epitaxy. DETAILED DESCRIPTION - The method for producing a semiconductor structural element (10), in which one-dimensional electron gas is developed, comprises providing a substrate (11) having a first surface, separating a masking layer having a first surface and a second surface, where the second surface of the masking layer is arranged on the first surface of the substrate, introducing a trench in the masking layer extending to the first surface of the substrate, inserting a semiconductor material in the trench by chemical vapor deposition, metalorganic chemical vapor deposition or metalorganic vapor phase epitaxy, which contains a group III nitride, and removing the first masking layer. A first insulation layer (12) with a first side and a second side is additionally deposited before depositing the masking layer. The second side of the first insulation layer is arranged on the first side of the substrate and the second side of the masking layer is arranged on the first side of the first insulation layer. The introduction of the trench in the masking layer comprises applying a photo lacquer on the first side of the masking layer. The photo lacquer is structured using electron beam lithography, UV-lithography and/or nano-printing process. A partial surface of the photo lacquer and/or a partial surface of the masking layer are removed using gas-phase etching. The trench has a width of 40-110 nm. After removing the masking layer, a partial surface of the substrate and/or the first insulation layer lying below the semiconductor material is removed after the removal of the masking layer. In the masking layer, a first trench and a second trench are introduced, where the second trench is connected with the first trench. After the removal of the masking layer, a separating point (17) is introduced in the semiconductor material and contact elements (18a, 18b, 18c) and/or connection elements are introduced. The method further comprises overgrowing a partial surface of a semiconductor structural element with a second insulation layer having a first surface and a second surface, which is disposed on the first side of the first insulation layer, on the first surface of the substrate and/or on the semiconductor material, depositing a further masking layer with a first surface and a second surface, which is disposed on the first surface of the second insulation layer, introducing a trench in the further masking layer, which reaches up to the first surface of the second insulation layer, inserting a semiconductor material in the trench, which contains group III nitride, and removing the further masking layer. The process step for producing a multi-layered semiconductor structure is repeatedly carried out. An INDEPENDENT CLAIM is included for a semiconductor structural element. USE - Method for producing a semiconductor structural element such as field effect transistors, optical waveguides and/or nano-electromechanical systems. ADVANTAGE - The method ensures efficient production of the semiconductor structural element with high performance and high electrical resistance.
Language
de
Patenprio
DE 102009024311 A: 20090605