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Impact of the storage layer charging on random telegraph noise behavior of sub-50nm charge-trap-based TANOS and floating-gate memory cells

: Seidel, K.; Hoffman, R.; Naumann, A.; Paul, J.; Löhr, D.-A.; Czernohorsky, M.; Beyer, V.


Institute of Electrical and Electronics Engineers -IEEE-; IEEE Electron Devices Society; IEEE Reliability Society:
IEEE International Integrated Reliability Workshop, IRW 2010 : Final report, S. Lake Tahoe, California, USA, 17 - 21 October 2010
Piscataway/NJ: IEEE, 2010
ISBN: 978-1-4244-8521-5
ISBN: 978-1-4244-8524-6
ISBN: 1-4244-8521-5
International Integrated Reliability Workshop (IRW) <2010, Lake Tahoe/Calif.>
Fraunhofer CNT ()

With the transistor scaling in the deca-nanometer range the impact of Random Telegraph Noise (RTN) on device reliability has significantly increased. Randomly occuring capture and emission of electrons in Si/SiO2 interface traps is causing a threshold voltage Vth) fluctuation and thereore instable device operation. The RTn impact on reliability is more prominent on non -volatile memory cells as compared to digital CMOS circuits due to the increased bottom oxide thickness and the commonly used multi-level operation.