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Flexible, any-time fault tree analysis with component logic models

: Förster, Marc; Schneider, Daniel


IEEE Computer Society:
IEEE 21st International Symposium on Software Reliability Engineering, ISSRE 2010 : 1-4 Nov. 2010, San Jose, CA
Los Alamitos/Calif.: IEEE Computer Society, 2010
ISBN: 978-1-4244-9056-1
ISBN: 978-0-7695-4255-3
International Symposium on Software Reliability Engineering (ISSRE) <21, 2010, San Jose/Calif.>
Fraunhofer IESE ()
embedded system; Fault Tree Analysis (FTA); model-based software development; safety; software

This article presents a novel approach to facilitating fault tree analysis during the development of software-controlled systems. Based on a component-oriented system model, it combines second-order probabilistic analysis and automatically generated default failure models with a level-of-detail concept to ensure early and continuous analysability of system failure behaviour with optimal effort, even in the presence of incomplete information and dissimilar levels of detail in different parts of an evolving system model. The viability and validity of the method are demonstrated by means of an experiment.