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Analysis of trap mechanisms responsible for Random Telegraph Noise and erratic programming on sub-50nm floating gate flash memories

: Seidel, Konrad; Hoffmann, Raik; Löhr, Daniel-Andre; Melde, Thomas; Czernohorsky, Malte; Paul, Jan; Beug, M. Florian; Beyer, Volkhard


IEEE Electron Devices Society; Boise State University; Snake River Chapter American Chemical Society; California Institute of Technology Jet Propulsion Laboratory; United States, Air Force, Office of Scientific Research -AFOSR-:
10th Annual Non-Volatile Memory Technology Symposium, NVMTS 2009. Proceedings : October 25-28, 2009 Portland Portland, OR
Piscataway, NJ: IEEE, 2009
ISBN: 978-1-4244-4953-8
ISBN: 978-1-4244-4954-5
Non-Volatile Memory Technology Symposium (NVMTS) <10, 2009, Portland/Or.>
Fraunhofer CNT ()

In this work we present a systematic investigation concerning the correlation of Random Telegraph Noise (RTN) with erratic bits in sub-50 nm floating gate NAND memory cells. Both effects are compared with respect to their implication in reliability and cell operation parameters of sub-50 nm flash devices. Related measurements were performed on a test chip with large floating gate cell arrays in NAND architecture. The analysis methods for both effects are presented comparing the magnitude and cycling stress dependency in detail. Additionally, two integration concepts with different memory cell sidewall oxidation approaches are discussed effecting differently the RTN and erratic programming behavior. Based on the characterization results we conclude that both effects are originating from different trap mechanisms. Possible explanations for the different trap mechanisms and locations are discussed.