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107-112 Gbit/s fully integrated CDR/1:2 DEMUX using InP-based DHBTs

: Makon, R.E.; Driad, R.; Schubert, C.; Fischer, J.; Lösch, R.; Walcher, H.; Rosenzweig, J.; Schlechtweg, M.; Ambacher, O.

5th European Microwave Integrated Circuits Conference, EuMIC 2010. Proceedings : 27-28 September 2010, Paris, France, European Microwave Week 2010
London: Horizon House, 2010
ISBN: 978-2-87487-017-0
ISBN: 978-1-424-47231-4
European Microwave Integrated Circuits Conference (EuMIC) <5, 2010, Paris>
Fraunhofer IAF ()
Fraunhofer HHI ()

This paper presents a monolithically integrated clock and data recovery (CDR) circuit with 1:2 demultiplexer (DEMUX), which is capable of processing signals with data rates between 107 Gbit/s and 112 Gbit/s. The fabrication of the integrated circuit (IC) relies on an in-house InP double heterostructure bipolar transistor technology (DHBT) featuring cut-off frequency values of more than 350 GHz for both fT and fmax. The CDR concept is based on a half-rate circuit architecture, whose main components are a linear phase detector including a 1:2 DEMUX, a voltage controlled oscillator (VCO), and a loop filter. Mounted into a module, the CDR/1:2 DEMUX features proper operation at data rates up to 112 Gbit/s, whereas the recovered and demultiplexed data exhibit clear eye opening and a voltage swing of 500 mVpp. The half-rate clock signal extracted from the input data features a voltage swing of 250 mVpp. By using the CDR module in an optical system environment, a bit error rate (BER) well below 10-10 is obtained at 112 Gbit/s with a data word length ranging up to 231-1.