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Fast mixed-mode PLL simulation using behavioral baseband models of voltage-controlled oscillators and frequency dividers

 
: Harasymiv, I.; Dietrich, M.; Knöchel, U.

:
Postprint urn:nbn:de:0011-n-1427595 (173 KByte PDF)
MD5 Fingerprint: cb8c17d680b4e5f4da917671db8a5735
© 2010 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Erstellt am: 14.10.2010


Institute of Electrical and Electronics Engineers -IEEE-:
XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design, SM2ACD 2010 : October 4-6, 2010, Gammarth, Tunisia
New York, NY: IEEE, 2010
ISBN: 978-1-4244-6816-4
ISBN: 1-4244-6816-7
ISBN: 978-1-4244-6815-7
6 S.
International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD) <11, 2010, Gammarth>
Englisch
Konferenzbeitrag, Elektronische Publikation
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()
phase-locked loop; N-integer frequency synthesizer; passband; baseband; signal; behavioral model; Verilog-A; spice-like simulator

Abstract
This article presents a new approach to fast mixed-mode simulation of phase-locked loops (PLLs) in time domain using Spice-like simulators and behavioral Verilog-A baseband (BB) models of voltage-controlled oscillators (VCO) and frequency dividers (FD). Other PLL blocks like phase-frequency detectors (PFD), charge pumps (CP), and loop filters (LP) can be transistor level and/or behavioral models. The use of both VCO and FD BB models in mixed-mode test bench allows fast PLL simulation and optimization of modern sophisticated PFD and CP blocks on transistor level with speedups of about 2-3 orders of magnitude.

: http://publica.fraunhofer.de/dokumente/N-142759.html