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1983
Conference Paper
Titel
Floating point computation in digital signal processing
Abstract
Recent advances in technology of VLSI circuits enables economical hardware implementation of highly sophisticated signal processing algorithms. This provides the capability of realizing a signal processor with uniform hardware for wide real-time applications. Arithmetics used in available integrated signal processors are based on fixed point number representation with wordlengths for the signals between 12 and 20 bits. Although some of the signal processors can operate with double precision intermediate results the overall accuracy is not satisfactory in many applications. It turns out that the hardware expense in terms of chip complexity grows more than proportional with increasing accuracy in the case of fixed point arithmetic. The economical solution for this problem is floating point number representation and arithmetic. This is outlined along three major items: (1) arithmetic operations in dyadic number systems; (2) advantages of floating point arithmetic compared to fixed point arithmetic; (3) floating point number formats and arithmetic units.
Language
English