Hier finden Sie wissenschaftliche Publikationen aus den Fraunhofer-Instituten.

Stress-induced phenomena in nanosized copper interconnect structures studied by x-ray and electron microscopy

: Zschech, E.; Huebner, R.; Chumakov, D.; Aubel, O.; Friedrich, D.; Guttmann, P.; Heim, S.; Schneider, G.


Journal of applied physics 106 (2009), Nr.9, Art. 093711, 5 S.
ISSN: 0021-8979
ISSN: 1089-7550
Fraunhofer IZFP, Institutsteil Dresden ( IKTS-MD) ()

We present the first dynamic study of damage mechanisms in nanosized on-chip Cu interconnects caused by stress-induced voiding in advanced integrated circuits. Synchrotron-based transmission x-ray microscopy is applied to visualize the void evolution and conical dark-field analysis in the transmission electron microscopy to characterize the Cu microstructure. Our x-ray microscopy measurements showed, in contradiction to electromigration studies, no void movement over large dimensions during the stress-induced void evolution. We observed in via/line Cu interconnect structures that voids are formed directly beneath the via, i.e., in the Cu wide line at the edge of the via bottom. It is concluded that voids are originally formed at the site where eventually the catastrophic failure occurs. During stress migration tests, Cu atoms migrate from regions of low stress to regions of high tensile stress, and simultaneously, vacancies migrate along the stress gradient (within a limited range of some microns) in the opposite direction to the location where small vias connect wide Cu lines. The stress distribution and the driving forces for atomic transport depend strongly on the particular geometry of the tested structure but also on interface bonding and metal microstructure. Vacancies form agglomerates and subsequently voids that grow further. The void growth rate depends on the Cu thin film material and its microstructure, particularly the grain size and the grain orientations. The Cu microstructure in the surroundings of the formed void shows that Cu grains are predominantly (111) oriented relatively to the wafer surface. Interfaces and grain boundaries, and particularly their orientation, determine the void evolution dynamics.