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Signal processor SIPRO23 with minimized overhead

: Selinger, T.; Talmi, M.

IEEE Acoustics, Speech, and Signal Processing Society -ASSP-:
ICASSP '89. Vol.2: S2D, Speech processing 2, digital signal processing : International Conference on Acoustics, Speech and Signal Processing, 23 - 26 May 1989 Glasgow, Scotland
Piscataway, NJ: IEEE, 1989
International Conference on Acoustics, Speech and Signal Processing (ICASSP) <14, 1989, Glasgow>
Fraunhofer HHI ()
cmos integrated circuits; digital signal processing chips; signal processor; sipro23; data addressing; digital signal processing; throughput; cmos technology; chip area; cycle time; architecture; processor components; dsp algorithms; 2 micron; 130 ns

The architecture of SIPRO23 was designed with special attention to the problems of data addressing in DSP (digital signal processing) algorithms in order to achieve increased throughput. The realization of SIPRO23 with 2- mu m CMOS technology requires 121 mm2 of chip area. The cycle time is estimated on the basis of simulations to be 130 ns. The derivation of the architecture and the processor components from DSP algorithms is explained.