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2010
Conference Paper
Titel
Sensitivity of a 20-GS/s InP DHBT latched comparator
Abstract
We present simulations and measurements of the sensitivity of a master-slave emitter-coupled logic (ECL) latched comparator implemented in an InP/GaInAs DHBT technology. The circuit exhibited simulated and experimental sensitivities of 11.5 mV and 17 mV, respectively, at a clock rate of 20 GHz, with no preamplifier.
Author(s)