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Parallel architecture and VLSI implementation of a 80 MHz 2D-DCT/IDCT processor

 
: Liebsch, W.; Boettcher, K.

Halaas, A. ; International Federation for Information Processing -IFIP-:
VLSI 91. Proceedings of the IFIP TC10/WG 10.5 International Conference on Very Large Scale Integration : Edinburgh, Scotland, 20 - 22 August 1991
Amsterdam: North-Holland, 1992 (IFIP Transactions A, Computer Science and Technology 1)
ISBN: 0-444-89019-X
S.267-275
International Conference on Very Large Scale Integration (VLSI) <6, 1991, Edinburgh>
Englisch
Konferenzbeitrag
Fraunhofer HHI ()
cmos integrated circuits; digital signal processing chips; high definition television; parallel architectures; transforms; video signals; vlsi; vlsi implementation; parallel architecture; cmos technology; two-dimensional discrete cosine transform; HDTV data reduction systems; video sampling rates; distributed arithmetic; idct circuit; full-custom vlsi; high-speed operation; 1.5 micron

Abstract
A parallel architecture and the implementation in CMOS technology is presented for high-speed forward and inverse two-dimensional discrete cosine transform. These circuits are applicable in advanced television and HDTV data reduction systems working at video sampling rates up to 80 MHz. The architecture utilizes the advantage of parallel and distributed arithmetic to achieve high-speed performance. An IDCT circuit is realized in 1.5 mu m CMOS technology as a full-custom VLSI component. It performs 720 million multiplications and 1280 million additions per second at nearly floating point precision for the 8 bit output values. The device demonstrates the transfer of a parallel and regular architecture for high-speed operation into a VLSI full-custom chip layout.

: http://publica.fraunhofer.de/dokumente/N-13681.html