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VLSI encoder/decoder chip for digital HDTV recording

: Hofker, U.; Stammnitz, P.; Talmi, M.

Dubois, E. ; European Association for Signal Processing -EURASIP-:
Signal processing of HDTV, IV : Proceedings of the International Workshop on HDTV '92, Kawasaki, Japan, November 18 - 20, 1992
Amsterdam: Elsevier, 1993
ISBN: 0-444-81551-1
International Workshop on HDTV <1992, Kawasaki, Japan>
Fraunhofer HHI ()
cmos integrated circuits; codecs; decoding; digital signal processing chips; high definition television; image coding; vlsi encoder/decoder chip; digital HDTV recording; HDTV signals; eureka standard; codec; digital vcr; data rate reduction; variable length coding and decoding chip; 0.8 micron; 1.152 Gbit/s

For the purpose of digital recording of HDTV signals (EUREKA standard, 1250/50/2:1) a codec has been realized (HDI-codec) which can reduce the initial data rate from 1.152 GBit/s down to one fifth. According to the desired reduction, the playtime of a digital VCR (video cassette recorder) can be increased from about 40-60 minutes up to at least the length of a feature film. In this paper one main component of the data rate reduction procedure is described. A variable length coding and decoding chip, based on a 0.8 mu m CMOS gate array.