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VLSI realization of a hierarchical MPEG-2 TV and HDTV decoder

 

Katsaggelos, A.K. ; Society of Photo-Optical Instrumentation Engineers -SPIE-, Bellingham/Wash.; IEEE Circuits and Systems Society; European Association for Signal Processing -EURASIP-:
Visual communications and image processing '94. Vol.3 : 25 - 29 September, Chicago, Illinois
Bellingham/Wash.: SPIE, 1994 (SPIE Proceedings Series 2308)
ISBN: 0-8194-1638-X
S.1734-1741
Conference on Visual Communications and Image Processing (VCIP) <1994, Chicago/Ill.>
Englisch
Konferenzbeitrag
Fraunhofer HHI ()
built-in self test; digital signal processing chips; digital television; hardware description languages; high definition television; logic design; video coding; video equipment; vlsi; vlsi realization; hierarchical mpeg-2 HDTV video decoder; spatially scalable profile; heinrich-hertz-institut; hierarchical digital tv transmission; HDTVt; tv-HDTV compatibility; terrestrial broadcasting; graceful degradation; portable reception; spatial scalability; snr scalability; integrated hardware solution; overall system architecture; logic synthesis; board dsp based functional test; multi-chip HDTV decoders

Abstract
This paper reports on the VLSI realization of a hierarchical MPEG-2 HDTV video decoder based on the spatially scalable profile at high-1440 level (SSP@H-14L). The decoder was conceived at the Heinrich-Hertz-Institut (HHI) within the ongoing joint R&D project "Hierarchical digital TV transmission" (HDTVT) and will be demonstrated during the international exhibition IFA 1995 in Berlin. One goal of the project is the demonstration of a compatible approach to HDTV with TV-HDTV compatibility through spatial scalability. The decoder can be used within several scenarios among which are terrestrial broadcasting with graceful degradation and portable reception (through spatial and SNR scalability) besides the less demanding cable and satellite scenarios. Two chips are currently under development to achieve an integrated hardware solution for the hierarchical MPEG-2 video source decoder. These chips are presented and the overall system architecture chosen for the HDTVT decoder is explained. The design approach utilises logic synthesis and an on board DSP based functional test is implemented to support the field trials. The paper shows that multi-chip HDTV decoders are feasible today. According to the technological progress being expected within the years to come, optimised single-chip decoders with less external memory can be realised until about 1998.

: http://publica.fraunhofer.de/dokumente/N-13448.html