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High performance reconfigurable multi-processor-based computing on FPGAs

: Göhringer, D.; Becker, J.

Postprint urn:nbn:de:0011-n-1342474 (772 KByte PDF)
MD5 Fingerprint: 0271bb23fd4a602ead14c4813fdc63c3
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Erstellt am: 25.11.2010

Institute of Electrical and Electronics Engineers -IEEE-; IEEE Computer Society:
IEEE International Symposium on Parallel & Distributed Processing Workshops and Phd Forum, IPDPSW 2010. Vol.2 : Atlanta, Georgia, USA, 19 - 23 April 2010
Piscataway, NJ: IEEE, 2010
ISBN: 978-1-4244-6533-0
ISBN: 978-1-4244-6534-7
ISBN: 1-4244-6533-8
International Parallel and Distributed Processing Symposium (IPDPS) <24, 2010, Atlanta/Ga.>
Konferenzbeitrag, Elektronische Publikation
Fraunhofer IOSB ()
Multiprocessor System-on-Chip (MPSoC); dynamic and partial reconfiguration; Field Programmable Gate Array (FPGA); design methodology; image processing

Multi-processor architectures are a promising solution to provide the required computational performance for applications in the area of high performance computing. Multi- and many-core Systems-on-Chip offer the possibility to host an application, partitioned in a number of tasks, on the different cores on one silicon die. Unfortunately, a partitioning of the tasks near to the performance optimum is the challenge in this domain and often a show-stopper for the success story of multi- and many-core hardware. The missing feature of these architectures is runtime adaptivity of the underlying hardware, which offers to tailor the hardware to the application in order to meet the task mapping process coming from top-down development. Especially, this Meet-in-the- Middle solution offers the novel hardware and software approach of RAMPSoC, which is described in this paper.