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Fast dynamic and partial reconfiguration data path with low hardware overhead on Xilinx FPGAs

: Hübner, M.; Göhringer, D.; Noguera, J.; Becker, J.

Postprint urn:nbn:de:0011-n-1342386 (400 KByte PDF)
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Erstellt am: 25.11.2010

Institute of Electrical and Electronics Engineers -IEEE-; IEEE Computer Society:
IEEE International Symposium on Parallel & Distributed Processing Workshops and Phd Forum, IPDPSW 2010. Vol.1 : Atlanta, Georgia, USA, 19 - 23 April 2010
Piscataway/NJ: IEEE, 2010
ISBN: 978-1-4244-6533-0
ISBN: 978-1-4244-6534-7
ISBN: 1-4244-6533-8
International Parallel and Distributed Processing Symposium (IPDPS) <24, 2010, Atlanta/Ga.>
Reconfigurable Architectures Workshop (RAW) <17, 2010, Atlanta/Ga.>
Konferenzbeitrag, Elektronische Publikation
Fraunhofer IOSB ()
Dynamic and partial processor reconfiguration; FPGA; internal configuration access port (ICAP); processor adaptation

Dynamic and partial reconfiguration of Xilinx FPGAs is a well known technique in runtime adaptive system design. With this technique, parts of a configuration can be substituted while other parts stay operative without any disturbance. The advantage is the fact, that the spatial and temporal partitioning can be exploited with the goal to increase performance and to reduce power consumption due to the re-use of chip area. This paper shows a novel methodology for the inclusion of the configuration access port into the data path of a processor core in order to adapt the internal architecture and to re-use this access port as data- sink and source. It is obvious that the chip area, which is utilized by the hardware drivers for the internal configuration access port (ICAP), has to be as small as possible in comparison to the application functionality. Therefore, a hardware design with a small footprint, but with an adequate performance in terms of data throughput, is necessary. This paper presents a fast data path for dynamic and partial reconfiguration data with the advantage of a small footprint on the hardware resources.