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Improved high-temperature etch processing of high-k metal gate stacks in scaled TANOS memory devices

: Paul, Jan; Beyer, Volkhard; Czernohorsky, Malte; Beug, M. Florian; Biedermann, Kati; Mildner, Marcus; Michalowski, Pawel Piotr; Schütze, Enrico; Melde, Thomas; Wege, S.; Knöfler, Roman; Mikolajick, Thomas


Ronse, K.:
The 35th International Conference on Micro- and Nano-Engineering, MNE 2009 : September 28 -1 October, 2009, Ghent, Belgium
Amsterdam: Elsevier, 2010 (Microelectronic engineering 87.2010, Nr.5-8)
ISSN: 0167-9317
International Conference on Micro and Nano Engineering (MNE 2009) <35, 2009, Ghent>
Konferenzbeitrag, Zeitschriftenaufsatz
Fraunhofer CNT ()

Reactive ion etching using BCl3-based plasma chemistries is a promising technique to pattern high-k metal gate stacks. High-k materials for non-volatile memory and CMOS applications, in particular Al2O3, possess high chemical resistance. Accordingly, a steep sidewall angle at the device edges is difficult to achieve by reactive ion etching. Advanced etch conditions at elevated temperatures (above 250 degrees C) is an alternative to solve this challenge but generate various other technological difficulties. In particular the patterning of TANOS devices reveals severe etch damage effects at the metal gate layer. A study of damage protection has been carried out and in particular the chemical stability of different metal gate options during plasma treatments was investigated in detail. Advanced process approaches to prevent the metal gate deterioration are proposed.