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Reduced on resistance in LDMOS devices by integrating trench gates into planar technology

Verringung von RDS,on in LDMOS-Bauelementen durch Integration von Grabengates in planare Technologie
: Erlbacher, T.; Bauer, A.J.; Frey, L.

Postprint urn:nbn:de:0011-n-1314491 (1.5 MByte PDF)
MD5 Fingerprint: 2f59b27802ef25956ed86fcca074b771
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Erstellt am: 10.7.2010

IEEE Electron Device Letters 31 (2010), Nr.5, S.464-466
ISSN: 0741-3106
ISSN: 0193-8576
Zeitschriftenaufsatz, Elektronische Publikation
Fraunhofer IISB ()
integrierte Schaltung; Smart-Power ICs; Leistungselektronik; Trockenätzprozeß; Leistungs-MOSFET

In this letter, we report on the reduction of device resistance by up to 36% in lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistors by incorporating trench gates into conventional planar technology. The process and device simulations of this novel device topology are based on a state-of-the-art LDMOS field-effect transistor with a reduced-surface-field extension (buried p-well) for high-voltage applications used for standard IC and ASIC manufacturing processes. Because the well implants can remain unchanged, only a few additional process steps are required for manufacturing such a device. By a straightforward combination of trench- with planar-gate topology, the device resistance can be reduced from 145 to 94 m Omega . mm(2) for the underlying 50-V LDMOS device while fully maintaining its specified blocking properties. The depth of the trench gates just slightly influences the electrical device properties, demonstrating the robustness of trench- gate integration into an existing planar-gate technology.