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Test Circuits for Fast and Reliable Assessment of CDM Robustness of I/O stages

: Stadler, W.; Esmark, K.; Reynders, K.; Zubeidat, M.; Graf, M.; Wilkening, W.; Willemen, J.; Qu, N.; Mettler, S.; Etherton, M.; Nuernbergk, D.; Wolf, H.; Gieser, H.; Soppa, W.; Heyn, M. de; Natarajan, M.I.; Groeseneken, G.; Morena, E.; Stella, R.; Andreini, A.; Litzenberger, M.; Pogany, D.; Gornik, E.; Foss, C.; Konrad, A.; Frank, M.

IEEE Electron Devices Society:
25th Electrical Overstress/Electrostatic Discharge Symposium 2003. Proceedings : Las Vegas, Nevada, September, 21 - 25, 2003
Rome, NY: ESD Association, 2003
ISBN: 1-585-37057-6
ISBN: 978-1-5853-7057-3
Annual International Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD) <25, 2003, Las Vegas/Nev.>
Fraunhofer IZM ()

CDM hardening during the development of technology, devices, libraries and finally products differs significantly from the process well-established for HBM. This paper introduces a method on the basis of specialized CDM test structures including protection elements and sensitive monitor elements. These test structures mimic typical CDM-sensitive circuits found by physical failure analysis over the years. Manufactured in five different technologies, structures were assembled in both a regular package and a new package emulator. CDM stress tests, vf-TLP tests, backside laser interferometry, device simulation, and failure analysis lead to new insights in the complex interdependencies during CDM and underline the need of CDM-specific test structures.