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Novel Hermetic WLP Technology using Low-Temperature Passivation

: Töpper, M.; Leib, J.; Mund, D.

Electronic Components, Assemblies, and Materials Association; Electronic Industries Alliance -EIA-; IEEE Components, Packaging, and Manufacturing Technology Society:
55th Electronic Components & Technology Conference 2005. Proceedings. Vol.1 : Lake Buena Vista, FL, USA, May 31 - June 4, 2005
Piscataway, NJ: IEEE Service Center, 2005
ISBN: 0-7803-8906-9
ISBN: 0-7803-8907-7
Electronic Components and Technology Conference (ECTC) <55, 2005, Lake Buena Vista/Fla..>
Fraunhofer IZM ()

In the past decade wafer level packaging (WLP) has been proven to be a very competitive solution regarding
performance, miniaturization and costs for a wide range of applications. However, they are up to now not matching the
performance of hermetically sealed Glass or Glass-to-Metal-Seal packages, esp. when considering application in extreme
environment. In this paper a novel packaging technology is proposed, allowing hermetic passivation and encapsulation of
microelectronic devices on wafer-level. This technology combines the unique properties of microstructuring of glass
on silicon process [1] with the capabilities of a wafer-level packaging technology using Silicon-Via-Contacts [2]. This
new processing technology is enabling hermetic encapsulation of devices on wafer-level comprising an unique, cost effective passivation process performed at temperatures below 120°C.