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Algorithm for the Automatic Verification of Complex Mixed-Signal ICs regarding ESD-Stress

Algorithmus zur automatischen Verifikation komplexer Mixed-Signal ICs gegenüber ESD-Belastungen
: Morgenstern, H.; Groos, G.; Köhne, H.; Reichl, H.


Ecole Polytechnique Federale de Lausanne -EPFL-; IEEE Circuits and Systems Society:
2005 PhD research in microelectronics and electronics. PRIME, proceedings of the conference. Vol.2 : Lausanne, Switzerland, July 25 - 28, 2005
Piscataway, NJ: IEEE Operations Center, 2005
ISBN: 0-7803-9345-7
Conference PhD Research in Microelectronics and Electronics (PRIME) <1, 2005, Lausanne>
Fraunhofer IZM ()

In this publication, an algorithm is described which automates the verification of a com¬p¬lex integrated circuit (IC) with regard to the behavior under transient high voltage impulses (e.g. ESD). Here, the complexity of the whole circuit diagram is being reduced in a first step in order to carry out a transient simulation with high current simulation models time-efficiently in a second step. The nowadays usual manual extraction of the relevant circuit parts for such a transient analysis is then automated and therefore, the error susceptibility of this process is minimized as well. The algorithm is embedded in a commercial design frame¬work for IC-design and uses the data structures already existing.