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Impact of technological options for 22 nm SOI CMOS transistors on IC performance

 
: Burenkov, A.; Kampen, C.; Bär, E.; Lorenz, J.

:
Preprint urn:nbn:de:0011-n-1174626 (137 KByte PDF)
MD5 Fingerprint: 6ca31f66f3d0f6d5fb15d25f3ba377a7
Erstellt am: 9.2.2010


Cristoloveanu, S.:
EUROSOI 2010, Sixth Workshop of the Thematic Network on Silicon on Insulator Technology, Devices and Circuits. Proceedings : 25-27 January, 2010, Grenoble, France
Grenoble, 2010
S.43-44
EUROSOI Conference <6, 2010, Grenoble>
Workshop of the Thematic Network on Silicon on Insulator Technology, Devices and Circuits <6, 2010, Grenoble>
Englisch
Konferenzbeitrag, Elektronische Publikation
Fraunhofer IISB ()
SOI MOS transistor; process simulation; device simulation; interconnect simulation; SPICE model; SRAM cell

Abstract
Technological performance boost options for 22 nm fully depleted SOI transistor based CMOS circuits were studied by means of TCAD and SPICE simulations. The impact of two different rapid thermal annealing (RTA) schemes, including spike annealing and flash annealing, on IC performance was investigated using recently advanced models. Mechanical stress was used to improve the electrical performance of PMOS transistors. Parasitic interconnect capacitances of a state of the art low-k inter-metal dielectric and air-gap structures were extracted from topography simulations and used in SPICE simulations to observe the dynamic performance differences.

: http://publica.fraunhofer.de/dokumente/N-117462.html