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Realisation of embedded-chip QFN packages - technological challenges and achievements

: Ostmann, A.; Manessis, D.; Böttcher, L.; Karaszkiewicz, S.; Reichl, H.

International Microelectronics and Packaging Society -IMAPS-, Italian Chapter; Institute of Electrical and Electronics Engineers -IEEE-:
EMPC 2009, 17th European Microelectronics and Packaging Conference & Exhibition. CD-ROM : June 15th-18th, 2009 , Rimini, Italy
New York, NY: IEEE, 2009
ISBN: 0-615-29868-0
ISBN: 978-0-615-29868-9
ISBN: 978-1-4244-4722-0
European Microelectronics and Packaging Conference and Exhibition (EMPC) <17, 2009, Rimini>
Fraunhofer IZM ()

The chip embedding technology achieved significant progress the last years. After various research activities the main focus is today on industrialisation and implementation of new business models. In the project HERMES European partners from industry and research aim to bring embedding technology based on low-cost PCB /Printed Circuit Board) processes to a market-ready product flow, demonstrated by automotive, power electronics and telecommunication applications. The research part of the project aims to overcome current limitations and to achieve even higher levels of miniaturisation. This paper will describe the embedding process flow and will discuss the process steps in detail. Three devices realised, a 2-chip module, a 3D System-in-Package and a QFN (Quad Flat No-Lead) package will be described and discussed. Especially the realisation of the QFN is a strong challenge for today's machine capabilities, since it contains a chip with a pitch of 100 mum.