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A 2D model for radiation-hard CMOS annular transistors

: Lopez, P.; Blanco-Filgueira, B.; Pardo, F.; Cabello, D.; Hauer, J.


Semiconductor Science and Technology 24 (2009), Nr.12, Art. 125009, 6 S.
ISSN: 0268-1242
ISSN: 1361-6641
Fraunhofer IIS ()

Scaling benefits of CMOS processes include the reduction of the oxide thickness, which in turn favors the reduction of threshold voltage shifts due to radiation-induced gate oxide trapped charge. Moreover, experimental results have shown that this inherent radiation hardness of deep submicron processes can be further exploited using gate-enclosed layout transistors with an annular design. For an in-depth analysis of such structures, we present in this paper a 2D analytical I-V model for short-channel annular devices based on the direct solution of the Poisson equation in cylindrical coordinates. The theoretical approach is confirmed with experimental data in a standard CMOS 0.18 mu m process.