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Reliability characterization and process optimization of Ni-based microinsert interconnections for flip chip die on wafer attachment
|Institute of Electrical and Electronics Engineers -IEEE-:|
IEEE 59th Electronic Components and Technology Conference, ECTC 2009. Vol.1 : San Diego, CA, USA, 26 - 29 May 2009
New York, NY: IEEE, 2009
|Electronic Components and Technology Conference (ECTC) <59, 2009, San Diego/Calif.>|
|Fraunhofer IWM ()|
| 3D interconnect; diagnostic; advanced packaging; multichip; failure analysis and models|
In many complex systems under development, the cost of integration and the compromises in performance that can result from the integration process can become prohibitive. Therefore, the establishment of a technology which enables the system level integration of devices from different technological families at the package level can become very attractive. In particular, since each component can be built in its optimum technology flow and interconnections within the package tend to be very short, very high performance can be achieved. The work to be presented in this paper describes direct and electrical reliability measurements of test structures used to optimise the electrical performance of micro insert based interconnection system as a function of flip chip mounting paramete rs. Micro-inserts have a great deal of potential for the face to face interconnection of stacked systems in three-dimensional integration technologies.