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Thermal simulation of defect localisation using lock-in thermography in complex and fully packaged devices

: Schmidt, C.; Naumann, F.; Altmann, F.; Martens, S.; Wilde, J.


Institute of Electrical and Electronics Engineers -IEEE-:
10th International Conference on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, EuroSimE 2009 : Delft, Netherlands, 26 - 29 April 2009
New York, NY: IEEE, 2009
ISBN: 978-1-4244-4160-0
ISBN: 978-1-4244-4159-4
International Conference on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE) <10, 2009, Delft>
Fraunhofer IWM ()
Fraunhofer IWM ()

Failure analysis of complex microelectronic devices is of increasing importance to secure and improve the reliability, quality and manufacturing yield. Especially for complex and fully packaged devices non destructive testing methods for localisation of shorts and opens in the internal circuitry are required. For localisation of electrical active defects on integrated circuit level the technique of Lock-In-Thermography (LIT) was developed which additionally allows failure localization at fully packaged and complex devices. Own to heat transportation thought the package material a phase shift occurs between the electrical input signal and the measured thermal response. This phase shift can be used to determine the defect depth when the relationship is directly known. In first simulations th e principle of the lock-in-thermography was simulated and the phase shift as a function of the related defect mould compound thickness was determined. As a comparison a mould compound test sample was modified and the thickness was reduced stepwise. In a second simulation a stacked-die-device was constructed containing 2 different chip layers with point heat sources at each chip layer. Owing to the necessary heat conduction through the package material the measured temperature distribution offers a lower amount of temperature change and a smeared temperature distribution. An optimization of the applied lock-in-frequency is required. The higher the lock-in-frequency the better is the spatial resolution and therefore the failure localization. The lower the lock-in-frequency the higher is the signal-noise-ratio and therefore the sensitivity of the measuring system. Using the finite element modelling unknown defect depths be calculated using a measured phase shift and known device geometry. In addition the lock-in-frequency can by optimized for a given device geometry and assumed defect size. In this paper further developments of this techique are presented for application of non destructive defect localization in fully packaged microsystems. Due to the fact that most package materials are not IR-transparent, hot spots caused by internal electrical shorts can be detected only at the surface of the device. To measure the phase shift in dependence of the mold sample thickness a well defined local heat stimulation was used. In addition a finite element model was built and calibra ted using experimental results. With reducing the thickness of the mold compound and measuring the thermal response of the defect at the surface the behaviour between both phase and sample thickness can be described.