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3D integration technologies

 
: Ramm, P.; Klumpp, A.; Weber, J.; Taklo, M.M.V.

Institute of Electrical and Electronics Engineers -IEEE-:
2009 Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP : Rome, Italy, 1 - 3 April 2009. Technical presentations of 2 conferences - CAD, design and test, Microfabrication, integration and packaging
Piscataway, NJ: IEEE, 2009
ISBN: 978-1-424-43874-7
S.71-73
Symposium on Design, Test, Integration and Packaging of MEMS, MOEMS (DTIP) <2009, Rome>
Conference on CAD, Design and Test <2009, Rome>
Conference on Microfabrication, Integration and Packaging <2009, Rome>
Englisch
Konferenzbeitrag
Fraunhofer IZM-M

Abstract
3D integration is a key solution to the predicted performance problems of future ICs as well as it offers extreme miniaturization and cost-effective fabrication of More than Moore products (e.g. e-CUBES (R)). Through Silicon Via (TSV) technologies enable high interconnect performance at relatively high fabrication cost compared to 3D packaging. A post backend-of-line TSV process is introduced as optimized technology for More than Moore products: The ICV-SLID process enables 3D integration of completely fabricated devices. Reliability issues, as thermo-mechanical stress caused by TSV formation and bonding are considered. The technology choice for the e-CUBES automotive application demonstrator is described.

: http://publica.fraunhofer.de/dokumente/N-101804.html