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Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing

: Diaz-Madrid, J.-A.; Neubauer, H.; Hauer, J.; Domenech-Asensi, G.; Ruiz-Merino, R.

IEEE Computer Society:
Design, Automation and Test in Europe, DATE 2009. Proceedings. CD-ROM : 20 - 24 April 2009, Nice Acropolis, France
New York, NY: IEEE, 2009
ISBN: 978-3-9810801-5-5
Design, Automation and Test in Europe Conference (DATE) <2009, Nice>
Fraunhofer IIS ()

High performance analog-to-digital converters (ADC) are essential elements for the development of high performance image sensors. These circuits need a big number of ADCs to reach the required resolution at a specified speed. Moreover, nowadays power dissipation has become a key performance to be considered in analog designs, specially in those developed for portable devices. Design of such circuits is a challenging task which requires a combination of the most advanced digital circuit, the analog expertise knowledge and an iterative design. Amplifier sharing has been a commonly used technique to reduce power dissipation in pipelined ADCs. In this paper we present a partial amplifier sharing topology of a 12 bit pipeline ADC, developed in 0.35µm CMOS process. Its performance is compared with a conventional amplifier scaling topology and with a fully amplifier sharing one.