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Enclosed layout transistors in saturation

 
: Lopez-Martinez, P.; Hauer, J.; Blanco-Filgueira, B.; Cabello, D.; Ernst, J.; Neubauer, H.; Hauer, J.

:

García Loureiro, A. ; Institute of Electrical and Electronics Engineers -IEEE-:
Spanish Conference on Electron Devices, CDE 2009. Proceedings : February 11 - 13, 2009, Museo do Pobo Galego, Santiago de Compostela, Spain
Piscataway/NJ: IEEE, 2009
ISBN: 978-1-4244-2838-0
ISBN: 978-1-4244-2839-7
S.116-119
Spanish Conference on Electron Devices (CDE) <7, 2009, Santiago de Compostela>
Englisch
Konferenzbeitrag
Fraunhofer IIS ()

Abstract
The fabrication of radiation tolerant devices is an emerging field with multiple applications in the space and high-energy physics domains. The reduction of radiation-induced oxide trapped charge characteristic of deep submicron CMOS processes can be boosted if appropriate layout styles such as the gate-enclosed layout transistors are used. In this paper we will present an analytical I-V model of these devices in both the linear and saturation regions of operation and a comparison to experimental data from fabricated devices.

: http://publica.fraunhofer.de/dokumente/N-101434.html