English
Deutsch
Log In
Password Login
or
Log in with Fraunhofer Smartcard
Research Outputs
Projects
Researchers
Institutes
Statistics
Fraunhofer-Gesellschaft
Home
Fraunhofer-Gesellschaft
Artikel
Numerical simulation of time delay and cross-talk noise for the interconnect in VLSI circuits
Details
Full
Export
Statistics
Options
2000
Journal Article
Titel
Numerical simulation of time delay and cross-talk noise for the interconnect in VLSI circuits
Author(s)
Ruan, G.
Xiao, X.
Song, R.R.
Streiter, R.
Otto, T.
Gessner, T.
Zeitschrift
Acta Electronica Sinica
Language
English
google-scholar
View Details
Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM