Determination of residual stress in a ceramic multilayer chip capacitor

Surface mounted components are being used increasingly in electronics, but the manufacture and assembly cause numerous problems of mechanical reliability. This is a very complicated situation depending on the size of the electronic elements as well as on the material behaviour of the various joined components. The example of a ceramic multilayer chip capacitor illustrates these problems. Ceramic materials are used as substrate or construction materials in microelectronics, especially in those cases, where hight thermal, mechanical, and electrical loads occur. Cracks in ceramic capacitors limit assembly reliability and yields. These cracks manifest themselves as electrical defects like intermittent contact, less of capacitance and excessive leaking currents. In this connection, the generation and determination of definite residual stresses seem to be an appropriate means to reach optimum properties of such ceramics. Residual stresses in a ceramic multilayer chip capacitor caused by ther mal load during sintering can arise freom several sources: - thermal stresses within the ceramics, - stresses due to the different thermal expansion of the metal-electrode (and/or the termination) and the ceramics. The X-ray stress measuring method was applied to investigate a residual stress distribution in the surface layer of the ceramic (barium titanate) capacitor. In addition, the stress gradients were measured using different diffraction lines and various radiations. In a further step, the thermal and mechanically caused stresses under operating conditions can be superimposed on the experimentally determined residual stresses by the help of finite element calculations.