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Design on high performance GaAs latched comparator for data conversion applications

: Feng, S.; Seitzer, D.


Institute of Electrical and Electronics Engineers -IEEE-:
IEEE International Symposium on Circuits and Systems 1992. Proceedings
New York/N.Y.; Piscataway/N.J.: IEEE, 1992
ISBN: 0-7803-0593-0
ISBN: 0-7803-0594-9
ISBN: 0-7803-0595-7
pp.228-231 (Vol.1)
International Symposium on Circuits and Systems (ISCAS) <25, 1992, San Diego/Calif.>
Conference Paper
Fraunhofer IIS A ( IIS) ()
circuit theory; comparator; HEMT; high electron mobility transistor; Komparator; Schaltungstheorie

Design considerations for high-speed and high-precision latched comparators in data conversion applications are presented in this paper. The comparators are built using a fully differential broadband amplifier and source coupled FET logic (SCFL) flip-flops in cascade. The limitations due to the DC offset voltage, settling time and voltage gain of the input differential amplifier and the regeneration and recovery times of the SCFL flip-flop are discussed for GaAs E/D FET technology. As a result, a high performance latched comparator has been implemented in a 0.5 mu m HEMT technology. Its measured input sensitivity voltage has reached 2.0 mV at 1.0 GHz and 10.0 mV at 4.0 Ghz.