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Design automation of digital circuits for partially depleted SOI-technology
|Mayer, D.C.; Fossum, J.G.; Allen, L.; Yoshino, A.; Krause, S. ; IEEE Electron Devices Society:|
International SOI Conference 1996. Proceedings
Piscataway, N.J.: IEEE, 1996
|International SOI Conference <1996, Sanibel Island/Fla.>|
| Conference Paper|
|Fraunhofer IMS ()|
| digitale Schaltung; Entwurfsautomatisierung; SOI-Technologie|
Semicustom design is a highly efficient technique to implement digital systems and digital parts of mixed-mode systems. One of the major tasks is to provide a comprehensive library of reliable standard cells, which can be quickly adapted to a change in technology. So automatic tools are indispensible for fast and correct layout generation and cell characterization. This paper shows that it is possible to adapt commercially available layout generators to the specific needs of partially depleted (PD)-SOI-technologies with minimal area penalty. Therefore, the requirements of SOI-specific layout techniques are investigated. A design flow for automatic layout generation is proposed. An implementation is presented with a cell library created with this generator. Measurements of test circuitry at temperatures up to 390 deg C and supply voltages up to 10 V are shown.