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Patent
Title

Speichertest

Other Title
Memory operation and/or test involves forming a first test information item for memory cells depending on variable parameter associated with relevant cell, content of relevant cell.
Abstract
Die Erfindung betrifft ein Verfahren und eine Vorrichtung zum Betreiben und/oder Testen von Speichern, welche einen zeitsparenden Test von Halbleiterspeichern waehrend des laufenden Betriebs ermoeglichen. Bei dem Verfahren zum Testen von Speichern (2) mit Speicherzellen (1) wird zu den Speicherzellen (1) jeweils eine erste Pruefinformation in Abhaengigkeit von einem der jeweiligen Speicherzelle (1) zugeordneten variablen Parameter und einem Inhalt der jeweiligen Speicherzelle (1) gebildet.

; 

WO2003043022 A UPAB: 20030630 NOVELTY - The method involves forming a first test information item for the memory cells depending on a variable parameter associated with the relevant cell and an item within the contents of the relevant memory cell. The cells are expanded by writing the test information in a first phase and faults are detected in a second phase by forming a second test information item and comparing it with the first test information item. DETAILED DESCRIPTION - AN INDEPENDENT CLAIM is also included for the following: an arrangement with memories with memory cells with associated test information. USE - For operation and/or test of memories with memory cells. ADVANTAGE - Enables time-saving testing of semiconducting memories while running.
Inventor(s)
Mayer, F.
Merchant, K.
Link to Espacenet
http://worldwide.espacenet.com/publicationDetails/biblio?DB=worldwide.espacenet.com&locale=en_EP&FT=D&CC=DE&NR=10206189A
Patent Number
2001-10155531
Publication Date
2003
Language
German
Fraunhofer-Institut für Integrierte Schaltungen IIS  
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