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CORDIC realization of a DFT processor

 

Proceedings of the European Signal Processing Conference
Amsterdam, 1986
pp.1319-1322 : Tab.,Lit.
European Signal Processing Conference (EUSIPCO) <1986, The Hague>
English
Conference Paper
Fraunhofer IMS ()

Abstract
This contribution describes a proposed implementation of a DFT processor based on a modified Bluestein algorithm. It uses CORDIC elements to execute complex multiplications. The processor has been simulated using the digital circuit simulator HILO-2. (IMS)

: http://publica.fraunhofer.de/documents/PX-8705.html